Skip to content

dts: stm32h7rs: Add SDMMC support for STM32H7RS series #94965

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Closed
wants to merge 3 commits into from
Closed

dts: stm32h7rs: Add SDMMC support for STM32H7RS series #94965

wants to merge 3 commits into from

Conversation

bricle
Copy link
Contributor

@bricle bricle commented Aug 25, 2025

This PR adds SDMMC support for STM32H7RS series microcontrollers and enables it on two development boards.

Changes:

  • SoC support: Add SDMMC1 and SDMMC2 controller configurations for STM32H7RS series

    • Includes register addresses, clock sources, reset controls, and interrupt definitions

  • Board enablement: Configure SDMMC1 on supported boards:

    • ART-Pi2: 4-bit SD card interface with card detection
    • STM32H7S78-DK: 4-bit SD card interface with card detection

Clock Configuration:

Both boards use PLL2S as the kernel peripheral clock source:

  • PLL2S frequency: 150MHz
  • Clock divider: 15 (clk-div = 13 register value)
  • Resulting SDMMC clock: 10MHz

Hardware Features:

  • 4-bit bus width support
  • Card detection via GPIO

Testing Status:

  • ART-Pi2: Tested and verified working with zephyr/tests/drivers/disk/disk_performance:
*** Booting Zephyr OS build v4.2.0-2287-g5945a3fcd1eb ***
Running TESTSUITE disk_performance
===================================================================
Disk reports 124735488 sectors
Disk reports sector size 512
START - test_random_read
512 Byte IOPS over 64 random reads: 2354 IOPS
 PASS - test_random_read in 0.032 seconds
===================================================================
START - test_random_write
512 Byte IOPS over 64 random writes: 942 IOPS
 PASS - test_random_write in 0.218 seconds
===================================================================
START - test_sequential_read
Average read speed over one sector: 1081 KiB/s
Average read speed over 64 sectors: 2656 KiB/s
 PASS - test_sequential_read in 0.133 seconds
===================================================================
START - test_sequential_write
Average write speed over one sector: 481 KiB/s
Average write speed over 64 sectors: 2496 KiB/s
 PASS - test_sequential_write in 0.212 seconds
===================================================================
TESTSUITE disk_performance succeeded

------ TESTSUITE SUMMARY START ------

SUITE PASS - 100.00% [disk_performance]: pass = 4, fail = 0, skip = 0, total = 4 duration = 0.595 seconds
 - PASS - [disk_performance.test_random_read] duration = 0.032 seconds
 - PASS - [disk_performance.test_random_write] duration = 0.218 seconds
 - PASS - [disk_performance.test_sequential_read] duration = 0.133 seconds
 - PASS - [disk_performance.test_sequential_write] duration = 0.212 seconds

------ TESTSUITE SUMMARY END ------

===================================================================
PROJECT EXECUTION SUCCESSFUL
  • STM32H7S78-DK: Configuration based on hardware specifications (no physical board available for testing)

Note: I don't have access to the STM32H7S78-DK physical board, but the configuration should be correct based on the hardware documentation. If anyone could help test this board, it would be greatly appreciated, and I'm willing to make adjustments based on the test results.

@bricle bricle marked this pull request as ready for review August 25, 2025 14:23
@zephyrbot zephyrbot added the platform: STM32 ST Micro STM32 label Aug 25, 2025
@bricle bricle marked this pull request as draft August 26, 2025 05:56
@bricle bricle force-pushed the stm32h7rs_sdmmc branch 2 times, most recently from 7c61c6d to 27ed7a3 Compare August 26, 2025 11:42
@bricle bricle marked this pull request as ready for review August 26, 2025 11:42
@sonarqubecloud SonarQubeCloud
Copy link

Quality Gate Passed Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

@bricle
Copy link
Contributor Author

bricle commented Aug 26, 2025

The last two pushs fixed SDMM1 reset clock and disabled SDMMC_STM32_CLOCK_CHECK by default for STM32H7S78-DK. Thanks.

erwango
erwango requested changes Oct 7, 2025
View reviewed changes
Copy link
Member

@erwango erwango left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Sorry for late review, this PR felt through the cracks.
Minor comment, otherwise LGTM

@bricle
Copy link
Contributor Author

bricle commented Oct 7, 2025

rebased to main to fix ci issue, nothing else changed.

erwango
erwango previously approved these changes Oct 7, 2025
View reviewed changes
etienne-lms
etienne-lms previously approved these changes Oct 7, 2025
View reviewed changes
@bricle bricle closed this Oct 7, 2025
@bricle bricle reopened this Oct 7, 2025
@erwango
Copy link
Member

erwango commented Oct 8, 2025

@bricle Please rebase.

@bricle bricle dismissed stale reviews from etienne-lms and erwango via 38ae355 October 8, 2025 14:53
@bricle bricle marked this pull request as draft October 8, 2025 14:56
bricle added 3 commits October 8, 2025 23:13
@bricle
dts: stm32: stm32h7rs: Add sdmmc1 and sdmmc2 configuration
a927852 
Provide the soc configuration for sdmmc1 and sdmmc2 controllers.
This includes registers address, clocks, resets and interrupt line
details.

Signed-off-by: Shan Pen <[email protected]>
@bricle
boards: art_pi2: Add SDMMC1 configuration with PLL2 kernel clock
a9525d1 
Configure SDMMC1 with 4-bit bus width and card detection. Use PLL2S
as kernel peripheral clock (150MHz) divided by 15 to achieve 10MHz
SDMMC clock with clk-div = <13>.

Signed-off-by: Shan Pen <[email protected]>
@bricle
boards: st: stm32h7s78_dk: Add PLL2 configuration and SDMMC1 node
08ed8ba 
Configure SDMMC1 with 4-bit bus width and card detection. Use PLL2S
as kernel peripheral clock (150MHz) divided by 15 to achieve 10MHz
SDMMC clock with clk-div = <13>.

Signed-off-by: Shan Pen <[email protected]>
@bricle bricle marked this pull request as ready for review October 8, 2025 15:28
@bricle bricle requested review from erwango and etienne-lms October 8, 2025 15:28
@sonarqubecloud SonarQubeCloud
Copy link

sonarqubecloud bot commented Oct 8, 2025

Quality Gate Passed Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

@erwango
Copy link
Member

erwango commented Oct 9, 2025

Please rebase to fix CI, now that #97204 has been merged.

@bricle bricle marked this pull request as draft October 9, 2025 15:08
@bricle bricle closed this Oct 9, 2025
@bricle
Copy link
Contributor Author

bricle commented Oct 9, 2025

Closed by mistake, and somehow it can't be reopened, so I created a new one #97293 , sorry for the inconvenience

@bricle
Copy link
Contributor Author

bricle commented Oct 9, 2025

try to reopen

@etienne-lms etienne-lms mentioned this pull request Oct 9, 2025
Open
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@erwango erwango erwango approved these changes

@etienne-lms etienne-lms etienne-lms approved these changes

@djiatsaf-st djiatsaf-st Awaiting requested review from djiatsaf-st

@FRASTM FRASTM Awaiting requested review from FRASTM

@gautierg-st gautierg-st Awaiting requested review from gautierg-st

@GeorgeCGV GeorgeCGV Awaiting requested review from GeorgeCGV

@marwaiehm-st marwaiehm-st Awaiting requested review from marwaiehm-st

@mathieuchopstm mathieuchopstm Awaiting requested review from mathieuchopstm

Assignees

@erwango erwango

Labels
area: Boards/SoCs platform: STM32 ST Micro STM32
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
4 participants
@bricle @erwango @etienne-lms @zephyrbot